The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that does not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Circuits typically employ oscillators to generate clock signals, e.g., in frequency synthesizers, serializers, deserializers, etc. As circuit components are operated under different clock signals, phase synchronization among different local oscillator (LO) paths on one circuit chip or on multiple circuit chips is often required. A LO path usually includes a fractional-N PLL, e.g., the frequency of the output clock signal is equivalent to the frequency of the input clock signal multiplied by a non-integer value, and the distribution circuits include dividers and buffers. The dividers can sometimes introduce phase ambiguity among different PLLs although a reference clock is shared among the different PLLs.
For example, in a wireless multiple-input multiple-output (MIMO) system, multiple transmitting and receiving signal paths need to be in-phase. At times, different dividers are used at different MIMO channels, which introduce phase ambiguity such that phases of the transmission signals at the different MIMO channels are not aligned. Sometimes a single PLL is used to track and lock the phases of transmission signals for all MIMO channels so that phase is synchronized across different MIMO channels have. However, for circuits of a larger size, using one single PLL for all MIMO channels requires a significant amount of wiring. On the other hand, when multiple PLLs are used, phase synchronization between the multiple PLLs on one circuit chip or between PLLs on multiple circuit chips can sometimes be implemented through a shared reference clock such that the phases at different oscillator outputs of the different PLLs are synchronized. However, even when the multiple PLLs share the same reference clock, the individual divider at each PLL can still introduce an incoherent state to the phases, thereby resulting in phase ambiguities in the LO paths on the circuit chip.